Massively parallel processor architectures are a special form of highly scalable parallel computing units with local memory. The Grid-of-Processing-Cell (GPC) architecture was introduced by Prof Rainer Dömer (University of California Irvine) in 2022 on the basis of abstract processor cells. This architecture was initially analysed by him on the basis of abstract simulations of the hardware and software with regard to scalability and performance for several applications.
In 2023, a project group from the "Circuit Technology" workgroup successfully implemented the GPC architecture as an FPGA prototype based on RISC-V processors for the first time. To bring the joint research work together, Dömer spent two research semesters at the Heinz Nixdorf Institute in Paderborn from 2024. In this context, a highly scalable hardware/software development environment based on SystemC and Chipyard was created with the specialist group in order to transfer RISC-V-based GPC architectures from initial C++ implementations via SystemVerilog models into FPGA prototypes and chips. Parts of the development environment were also successfully migrated to the Noctua2 cluster of the Paderborn Centre of Parallel Computing (PC2) for simulation acceleration.
Since 2023, the "Circuit Technology" workgroup can look back on a very successful cooperation with UC Irvine and the PC2, with several publications at national and international conferences.
