Electronic System Design
Course No.: L.048.28503/L.048.98503
Type: Project group
Credits: 9+9
Semester: SS+WS
Schedule and Location: to be announced in PANDA
Short description
Design, Simulation and Synthesis of a digital RISC-V Based SoC.
Content
The project group introduces students to practical RISC-V-based processor design using the hardware configuration language Chisel. After an introduction to Chisel, simple digital circuits are designed using Chisel, Verilog code is generated, and the circuits are simulated using the Verilator RTL simulator. Subsequently, a RISC-V processor system based on the Rocket Chip architecture is extended, simulated, and synthesized for an FPGA.
Tasks
- Introduction to the Chisel hardware description language
- Generating Verilog using the RocketChip Generator
- Circuit design and simulation of digital components in Chisel
- Extending, simulation, and FPGA synthesis of a RISC-V-based processor system
Organization
Phase 1 (SS): Introduction to Chisel and Chipyard by the means of simple examples (Design, Simulation and Presentation)
Phase 2 (WS): Extending an existing Microprocessor System (Design, Simulation, Synthesis and Presentation)
Requirements
- Course „Computer Architecture“
- Basic Skills in VHDL or Verilog
- Basic Skills in FPGA-Synthese
- Basic Skills make, Shellskripte, Python
Teaching staff
M.Sc. Kai Arne Hannemann, M.Sc. Lars Luchterhandt, Prof. Wolfgang Müller