A reference-less 28 Gbps Non-Return-to-Zero (NRZ) full-rate Bang-Bang Clock and Data Recovery (BBCDR) circuit is demonstrated for high-speed optical transceivers. Implemented in IHP’s 250 nm SiGe BiCMOS (SG25H4) technology, the design is compatible with Electronic–Photonic Integrated Circuit (EPIC) integration. The architecture employs a transition-based nonlinear Alexander phase detector and a second-order Phase-Locked Loop (PLL) with an adaptive dual-loop filter, enabling robust clock recovery and data retiming. A key contribution is a frequency acquisition technique based on controlled offset-current modulation within the integral path, which intentionally detunes the VCO during operation. This approach significantly extends the acquisition range beyond conventional BBCDR designs with minimal complexity and power overhead. Continuous offset modulation further enables autonomous frequency acquisition, improving startup reliability and simplifying system integration.

References

[1] M. Iftekhar and J. C. Scheytt, “Enhanced pll circuit,” Patent WO2023099639A1, 2023.

[2] M. Iftekhar, S. Gudyriev, and J. C. Scheytt, “Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral Branch Offset Currents,” in 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2021, pp. 1–4.

[3] M. Iftekhar, S. Gudyriev, and J. C. Scheytt, “28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25um Photonic BiCMOS Technology,” in 2020 IEEE 20^th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),2020, pp. 26–29.