Brief description
In today's practice, the design of digital chips consists of the combined application of different languages, methods and tools for modelling, simulation and synthesis of electronic circuits. Along the modern abstraction level-based design flow of digital systems (electronic system level up to chip layout), the course provides basic knowledge of the essential description languages and their application in modelling, simulation, analysis and synthesis. This includes basic principles and application of the IEEE standard system/hardware description languages SystemVerilog, SystemC, Verilog and VHDL in conjunction with additional formats such as SDF and UPF for the annotation of time and power behaviour. In the application, the essential principles of test environments for simulation, time and power analysis, logic synthesis and the physical design of digital circuits. Exercises accompany the course using commercial tools from Mentor Graphics, Synopsys and Cadence Design Systems.
Contents
- VLSI Design Flow
- Electronic System Level Design
- Simulation Principles (SystemC, VHDL, SystemVerilog)
- Functional Verification & Testbenches
- Timing and Power Annotations
- RTL Modelling
- Static Timing Analysis
- Logic Synthesis
- Physical Design
- Floor Planning
- Power Network
- Clock Tree Synthesis
- Placement & Routing
- Sign-Off
