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Schumacher, Tobias;Suess, Tim;Plessl, Christian;Platzner, Marco:

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.

International Journal of Reconfigurable Computing 2011: S. 1--11, 2011 - Article ID 760954

Abstract

Reconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics. A key challenge for achieving high-performance with reconfigurable accelerators is the efficient utilization of the available memory resources. A detailed knowledge of the memories' parameters is key for generating an optimized communication layout. In this paper, we discuss a benchmarking environment for generating such a characterization. The environment is built on IMORC, our architectural template and on-chip network for creating reconfigurable accelerators. We provide a characterization of the memory resources available on the XtremeData XD1000 reconfigurable computer. Based on this data, we present as a case study the implementation of a 3D image compositing accelerator that is able to double the frame rate of a parallel renderer.

Weblink

doi:10.1155/2011/760954

Bibtex

@article{hniid=5253,
author = {Schumacher, Tobias and Suess, Tim and Plessl, Christian and Platzner, Marco},
title = {FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study},
journal = {International Journal of Reconfigurable Computing},
volume = {2011},
pages = {1--11},
year = {2011},
note = {Article ID 760954},
}

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https://www.hni.uni-paderborn.de/pub/5253