Iftekhar, Mohammed;Gudyriev, Sergiy;Scheytt, Christoph:

28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology.

In: 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Antonio, TX, USA, USA, Jan 26 - 29, 2020, IEEE

Abstract

A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 µm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies. Index Terms— Bang-bang phase detector, clock and data recovery, jitter transfer, jitter tolerance, optical receiver

Weblink

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9040190

Bibtex

@inproceedings{hniid=10203,
author = {Iftekhar, Mohammed and Gudyriev, Sergiy and Scheytt, Christoph},
title = {28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology},
booktitle = {2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)},
address = {San Antonio, TX, USA, USA},
publisher = {IEEE},
month = {26~-~29~} # jan,
year = {2020},
}

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Permalink

https://www.hni.uni-paderborn.de/pub/10203