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Adelt, Peer;Koppelmann, Bastian;Müller, Wolfgang;Scheytt, Christoph:

A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.

In: Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2020), Stuttgart, DE, Mar 2020

Abstract

Fault effect simulation is a well-established technique for the qualification of robust embedded software as required by different safety standards. Our article introduces a Virtual Prototype based approach for the efficient and fast fault effect simulation of compiled binary RISC-V software. The approach supports the different possible RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections by bitflips. A first analysis of a software binary gives the register and opcode type coverage and a few other statistics with respect to the supported ISA subset of the underlying RISC-V hardware platform followed by the generation of fault injected test programs as mutations. The final execution of all mutated binaries minimizes the number of execution runs by eliminating the redundant binaries from the testbench, i.e., keeping only those with an observable fault effect and different ISA and hardware coverages. Our evaluation results with automatic program generation demonstrate that QEMU provides an efficient platform for fault coverage and effect analysis.

Bibtex

@inproceedings{hniid=10022,
author = {Adelt, Peer and Koppelmann, Bastian and M{\"u}ller, Wolfgang and Scheytt, Christoph},
title = {A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures},
booktitle = {Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2020)},
address = {Stuttgart, DE},
month = mar,
year = {2020},
}

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https://www.hni.uni-paderborn.de/pub/10022