GigaNet Logo

Next generation networking technology

Information processing and networking of technical devices become more and more obvious in our daily life. To handle the constantly growing amount of data which has to be processed there is an increasing need for powerful routing nodes in the different networks. The aim of the GigaNetIC project is to develop high-speed components for networking applications and to explore new kinds of applications for massively parallel architectures.

In the beginning of the year 2002, a cooperation between Infineon Technologies, especially the department of Prof. Ramacher, the universities of Paderborn, Ulm, and the RWTH Aachen was founded with support of the BMBF. It is the aim of the project to develop super-high-speed components for communication and network applications as well as basic techniques for massively parallel systems. As a result of this approach a powerful network processor is to be developed that is also usable as a universal co-processor. A particular attraction of this project grounds on the interdisciplinary coupling of the different working groups that marked the project right from the beginning. In order to handle the upcoming data traffic of the future special, high-integrated circuits are needed for the network nodes. In the working group System and Circuit Technology (Prof. Rückert) such complex high-integrated components are beeing designed and produced. In this project, an architecture is beeing developed that is based on massively parallel processing enabled by a multitude of processors. The first step will be to generate a chip that consits of 32 processors. For this we will use the S-Core processor, a 32bit RISC processor core that has been developed by the System and Circuit Technology group. Infineon provides basic cells and the most up-to-date chip production technologies. These allow feature sizes of less than 130nm and make it possible to shrink the area needed for one S-Core to less than 0.2mm². Hence it is possible to integrate more than 1000 of these processors on the area of a one-cent coin. Another research focus is on on-chip networks that are needed for the immense data throughput on the chip.

For an efficient use of the massively parallel structure a special compiler is developed by the working group Programming Languages and Compilers (Prof. Kastens). The compiler has to process the software of the network processor in a way that each processing unit is optimally used and no unnecessary time is spent in idle states. Another task is to coordinate the involved hardware units and to provide an efficient performance of the system. Besides these classical tasks for the development of compilers, a network processor has to deal with a permanently growing bunch of protocols. Consequently the software for a network processor has to be adapted to new requirements within short periods of time e.g. to fulfill new security standards or quality criteria. New methods developed by the group of Prof. Kastens help to react very flexibly to these changing requirements and support the generation of powerful software out of compact specifications. For integrating a huge amount of processors on a single chip it has to be assured that these units are able to communicate efficiently with each other over an on-chip interconnection network. Design, analysis and evaluation of such networks and the appropriate communication protocols are main research interests of the group of Algorithms and Complexity (Prof. Meyer auf der Heide). Another topic is the analysis of the architecture used as an universal co-processor. Such a chip could speed up many applications through its inherent parallelism in a cost and power saving way. The chip integrated on a PC-Card could disburden the main CPU of the host system. To support the software developper special programming models and libraries are developed.