DERty RuSt

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The research team DERty RuSt concentrates on the development of design methodologies and optimization concepts for reconfigurable embedded systems in the hardware domain. We put our main focus on methods that allow an abstraction of the underlying and often cumbersome details of the reconfiguration. The ongoing research activities complement one another to a seamless design methodology, which is reflected in an integrated tool chain. Our methodology, which includes a model-based modeling approach, an automated synthesis process, and dynamic reconfiguration scheduling, enables us to benefit from the partial and complete hardware reconfiguration during runtime.

Our aim is to design optimized computer systems that involve reconfigurable hardware devices such as FPGAs (Field Programmable Gate Array). Depending on the characteristics of the application, such devices can overcome sequentially working processors in efficiency and performance by many times. Therefore, we extend existing technologies from the reconfigurable computing domain and apply them to perform dynamic reconfiguration at runtime. The development of innovative optimization strategies allows an efficient application of reconfiguration techniques.

Focusing on an increase of performance, the research team DERty RuSt explores design methods, which take advantage of the special properties of reconfigurable hardware devices and make them accessible for higher levels of abstraction. Thus, runtime systems like the DREAMS operating system, which is developed in our research team DERty DREAMS, possess the capability to manage the resources of a reconfigurable computing system and make them available to the applications. The combination of design methodology and runtime system should assure applications to be platform independent to the greatest possible extent and to maximize the advantage of runtime reconfiguration in compliance with given real-time constraints.

Partitioning

To compute applications that exceed the area constraints of the target hardware platform, we investigate methods for dynamic partitioning and dynamic placement. Therefore, we cluster input algorithms by means of several algorithms including spectral methods. After this modularization, we can load the partitioned algorithms consecutively into different slots, which are part of the same reconfigurable device. Our methods thereby reduce the inter-module communication requirements. The challenges resulting from this approach reach form an abstract modeling up to a realization in form of specific synthesis tools. The ongoing research is supported by the DFG priority program “Reconfigurable Computing”.

Caching and Pipelining

Reconfiguration involves costs that should be kept as low as possible. One possibility is to employ prefetching techniques that are used in pipelining systems. Thanks to the partial reconfiguration capability, we can reconfigure parts of our design while other parts are executed at the same time. Thereby, we interlock reconfiguration and execution phase (e.g., by manipulation of the execution frequency) in order to improve the overall response time of a system. In case of periodic systems, we can hold configurations on the device, i.e., we apply caching concepts. In detail, we prefer tasks for caching if they show a higher priority and thus are worthwhile for occupying some area for a longer time. Furthermore, we gain an advantage of the long reconfiguration phase by fundamentally integrating it into scheduling algorithms. Due to the single reconfiguration port only one area can be reconfigured at the same instance of time. This similarity to mono processors - where tasks are executed exclusively - allows us to broaden reconfigurable systems to hard real time scenarios by applying known concepts of mono processor scheduling.

Scheduling of Hardware Tasks

Embedded real-time systems are an important field of application for reconfigurable systems. To make the available hardware resources efficiently accessible for several processes, it is necessary to be able to exchange also processes, which are implemented in hardware. This is a time critical job, which requires a special scheduling to fulfill all given time limits. The challenge is to organize the execution of a set of periodic processes in such a way that all timing restrictions are satisfied. Therefore, each process is characterized by its execution time, its deadline and its requirements concerning resources like chip area. To solve this problem, we examined and adapted particular multi processor scheduling approaches. An analysis of these approaches allows the evaluation of the guaranteed performance, the practicability and the time overhead that results from the chip-reconfiguration. Our gained knowledge enables us to deploy multitasking in reconfigurable computing realtime systems. Currently, we develop an FPGA operating system prototype based on the server-based scheduling approach.

Hybrid Systems

Our research also focuses on development of methodologies and mechanisms for reconfigurable hybrid systems. These systems, comprising general purpose processor (GPP) and FPGA (Field Programmable Gate Array), are very attractive as they can provide flexibility as well as high computational performance to support today’s embedded systems requirements. Particularly, the usage of such hybrid-based architectures in changing (dynamic) environments is well suited. However, due to the intrinsic resource constraint of such architectures, an efficient usage of the available resources by the running tasks is needed. Therefore, algorithms for run-time evaluation of the resources values and dynamic assignment of the tasks to the proper execution environments (GPP or FPGA) have been developed. In this scenario, the system continuously evaluates the actual resource usage efficiency and, if necessary, it reconfigures the system for this purpose by means of redistribution of the tasks over the hybrid architecture. In addition, in the case of real-time systems, even with this temporarily reconfiguration activities, the timeliness of the current application must be respected. For this case, techniques from RTOS scheduling have been expanded and adapted.

Interface Synthesis and Applications

Interface Synthesis

Another important research aspect focuses on the modeling and automated synthesis of reconfigurable interfaces. These interfaces allow us to interconnect heterogeneous applications in an alterable communication system as we can find it in the IP (Intellectual Property) based design. The interface acts as transparent adapter module and is able to handle numerous applications in parallel (multi task interfaces). Due to the modular structure of the adapter, we can exchange individually connected applications during runtime by reconfiguration of the interface. Thereby, affected parts of the interface are reconfigured as well. This approach allows the exchange of applications in safety-critical real-time environments by guaranteeing a deterministic behavior even during the reconfiguration at runtime. Moreover, the modeling of complex communication systems with UML2.0 is handled by a dedicated tool, developed in our working group. A subsequent synthesis process generates the reconfigurable VHDL fragments of the adapting interface block which then may be placed by the tool mentioned above.

Applications

Another aspect of our methodology covers load balancing in heterogeneous clusters, where reconfigurable hardware is one part of the employed computing resources. Such approaches are promising in the field of high performance computing. Reconfigurable devices as parts of such systems have the potential to increase the performance, while still being flexible enough to meet changing computational requirements.